introduction

The ability to accurately digitize sine waves is a sensitivity test for the fidelity of high resolution AD converters. This test requires a sine wave generator with a residual distortion component of approximately 1 ppm. In addition, a computer-based AD output monitor is required to read and display the converter output spectral components. If you want to implement this test at a reasonable cost and complexity, you must design its components and perform performance verification before use.

summary

Figure 1 shows a schematic of the system. A low distortion oscillator drives AD through an amplifier. The AD output interface formats the converter output and communicates with the computer responsible for performing the spectrum analysis software and displaying the resulting data.

Figure 1 shows the schematic of the system

Oscillator circuit

The oscillator is the most difficult part of the circuit design in the system. In order to make meaningful tests on 18-bit AD, the oscillator must be ultra-low purity and these features must be verified in a separate way. Figure 2 is basically a “full-reverse” 2kHz Wien bridge design (A1-A2) based on research done by Harvard University's Winfield Hill. The original design of the J-FET gain control was replaced by an LED-driven CdS photocell isolator, eliminating the errors caused by J-FET conductivity modulation and eliminating the need to fine-tune these errors to the utmost. The band-limited A3 is responsible for receiving the A2 output and the DC offset offset and providing an output through a 2.6kHz filter to drive the AD input amplifier. The Automatic Gain Control (AGC) signal for the A1-A2 oscillator is derived from the circuit output ("AGC Detection"), which is responsible for feeding the rectifier A5-A6. The DC output of A6 represents the AC amplitude of the sine wave output from the circuit. This value is balanced with the LT-1029 reference using a current summing resistor terminated to AGC amplifier A7. A7 driving Q1 closes the gain control loop by setting the LED current (and thus the CdS photocell resistance) to stabilize the amplitude of the oscillator output. Although this attenuates the band-limited response of A3 and the output filter, gain control feedback from the output of the circuit maintains the output amplitude. In addition, it also requires the A7 loop closure dynamics. Specifically, the band limitation of A3, combined with the hysteresis of the output filter A6 and the ripple rejection component (in the base of Q1), can produce significant phase delays. A 1μF main pole on A7 along with an RC zero provides this delay for stable loop compensation. This approach replaces the tightly tuned high-order output filter with a simple RC roll-off filter to minimize distortion while maintaining output amplitude.

Figure 2 is basically a “full reverse” 2kHz Wien bridge design (A1-A2)

Eliminating oscillator-related components from the LED bias is key to maintaining low distortion. Any such residual noise will adjust the amplitude of the oscillator, thus introducing an impure component. The band-limited AGC signal forward path is well filtered, and the large RC constant in the Q1 base provides the ultimate steep roll-off. As shown in Figure 3 (the emitter current of Q1), the oscillator-dependent ripple is approximately 1nA (less than 0.1ppm) at a total current of 10mA.

As shown in Figure 3 (the emitter current of Q1), the oscillator-dependent ripple is about 1nA in the total current of 10mA.

The oscillator achieves its performance with only one fine-tuning. This adjustment, which determines the center of the AGC capture range, is set according to the schematic annotation.

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