One of the key characteristics of dynamic memory is that it requires periodic refreshing to retain data, as the stored information is volatile. In this system, the Timer 1 interrupt of the 8031 microcontroller is utilized to perform the necessary DRAM refresh operations. The following is the program code responsible for the timer interrupt refresh:
During the refresh process, Timer 1 is first configured. When the 8031 executes the instruction at address DEC 70H, it fetches the instruction from external program memory (EPROM), which activates the PSEN signal. At this moment, the T1 pin goes high, enabling the RAS signal. Simultaneously, the address of the instruction in EPROM is also sent to the DRAM. The lower 9 bits of the address are used as row addresses for the DRAM refresh. Since the DEC 70H instruction operates on internal RAM, no other addresses appear on the address bus. By continuously executing the DEC 70H instruction located at 0200H, the system can refresh a 1 MB DRAM, which requires 9-bit row addressing.
Once the interrupt routine is entered, the Timer 1 parameters are immediately reset, and the timer is re-enabled to maintain continuous timing. The input clock for Timer 1 is derived from the internal oscillator, with a frequency division factor of 1/12. For example, if a 12 MHz crystal is used, the effective counting rate becomes 1 MHz. With the initial value set to FFFFH - F63BH - 09C4H, the refresh cycle is approximately 2.5 ms. This is shorter than the standard 16 ms refresh period required by most 1 MB DRAMs, allowing the timer settings to be adjusted for longer intervals if needed.
For efficient data handling, the system employs a circular buffer management strategy. The main program sends data to the host computer while monitoring the head and tail pointers along with status flags to determine buffer availability. Data reception is handled via interrupts, ensuring that new data is received and the DRAM is refreshed simultaneously. To avoid conflicts, the interrupt priority for DRAM refresh should be set higher than the data receive interrupt, ensuring timely refresh operations without data loss or performance degradation.
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