Abstract: According to the high reliability requirements of large-screen industry applications, a dual-host redundant video display solution is designed. Utilizing the latest PCI Exrpess bus technology, a dual-master communication channel is built on the bridge chip PEX8696, and the host information is transmitted through the heartbeat register of the non-transparent bridge, thereby realizing the function of the slave-to-host work monitoring and achieving high reliability. Requirements. At the beginning of the system startup, a system state transition mechanism is designed to ensure the normal startup and operation of the redundant system. The analysis results show that the design mechanism of the video redundancy is reasonable, and the state transitions in the system are safe, which greatly improves the reliability of the system operation.
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Keywords: redundancy; non-transparent bridge; video display; PCI Express; PEX8696
The importance of redundant systems
In recent years, with the steady development of the domestic economy, various industries in various fields in China have attached great importance to the construction of information technology, and the demand for information visualization has also expanded dramatically, especially for the needs of some important places such as monitoring centers, command centers, and dispatch centers. There is an increasing demand for the size of the displayed image to be viewed, and more and more information is required for displaying the image. It is required to simultaneously display images and text information of a plurality of different information on an oversized screen. The images displayed by the various units of the screen enable seamless connection. With the continuous promotion of the application field of large-screen wall, the application in the fields of medical imaging, command and dispatch centers has generated high reliability requirements, and this demand is very urgent. For example, in clinical surgery, the interruption of medical images may threaten the lives of a patient, and these demands have prompted people to develop high-reliability video display systems.
The reliability of the system is reflected in many aspects, including component selection, derating design, and redundant design. Redundant system design, in order to be safe, adopts two sets of hardware and software of the same configuration. The purpose is that when one system fails, the other system can start immediately and replace the work, which is like the actor's substitute, two sets. A complete and easy-to-use system may have a high failure rate for individual operation, but after taking redundant measures, the stability of the system can be greatly improved without changing the internal design! If the failure rate of the individual system is 50 %, and the redundant system can immediately reduce the failure rate to 25%. This paper mainly considers the redundancy of the host, and aims to realize a video display system with backup function. The system will adopt PCI Express protocol and transparent bridge technology to realize dual-host redundancy design; PLX company's bridge chip PEX 8696 will be used to connect dual hosts to realize host backup function.
PCI Express bus
PCI Express is a new generation of bus interface. As early as the spring of 2001, Intel proposed to use a new generation of technology to replace the PCI bus and the internal connection of a variety of chips, and called the third generation I / O bus technology. It completely revolutionizes the parallel technology of the original PCI bus, and overcomes the defects of the PCI bus in terms of system bandwidth and transmission speed. Its superior performance meets the high speed and high reliability requirements of I/O data transmission in the computer and communication fields.
Compared with the original PCI bus, the PCI Express bus has the following features.
(1) In the data transmission mode, the PCIe bus adopts a dual channel serial transmission mode. A PCIe channel consists of two pairs of LVDS differential pairs. One pair is responsible for transmitting and one pair is responsible for receiving. Currently, the PCIe 2.0 unidirectional data rate is 5 Gbit/s.
(2) Unlike all buses on the PCI bus that do not share a bus, the PCIe bus uses point-to-point technology to allocate independent channel resources for all devices in the system, fully guarantee the bandwidth of the device, improve the data transmission rate, and achieve multiple The devices work in parallel.
(3) With great flexibility, a PCIe physical connection can be configured into ×1, ×2, ×4, ×8, ×16, ×32 parallel data channels according to actual needs to meet the communication between different devices. Bandwidth requirements.
(4) Fully compatible with the PCI bus at the software layer. The original bus driver can be fully ported to the PCIe bus architecture system.
(5) The serial connection adopts self-clock technology, and the clock is embedded in the 8-bit/10-bit encoding of serial data, which can realize adaptive adjustment of data transmission rate.
(6) Serial data is transmitted in the form of data packets, which ensures the integrity and reliability of data transmission.
In the field of large-screen splicing display, PCIe bus expansion technology is very critical because of the large number of display units and the need to access multiple data cards at the same time. With the transparent bridge chip, the expansion of the PCIe bus can be realized very conveniently. Our system requires a bridge chip that supports more PCIe lanes while supporting multi-master connectivity and fault tolerance. After researching several chip manuals, we found that PLX's PEX8696 chip is very suitable for the design requirements of this redundant system. The chip complies with the PCIe 2.0 specification [2] and is PCIe 1.1 compliant, including PCIe power management features; PCIe extensions supporting Base Mode and Visual Switch Mode; 96 PCIe channels Each channel has a maximum power of only 900mW; with 24 ports, the port channel can be flexibly configured, and supports balanced and unbalanced port configuration functions; supports multi-master functions and fault tolerance, including 1+1 fault tolerance and N+1 fault tolerance. Function; non-blocking chip architecture, PIPE packet exchange time is less than 150ns; support non-transparent bridge function; flexible configuration, support hard connection configuration, EEPROM configuration, SMBUS (system management bus) configuration and host software configuration four ways. Figure 1 shows the internal module of the PEX8696 chip [2]. From the figure, we can see that the 96 PCIe channels of the chip are in 6 stations, each station is independent, connected by the internal fabric; the logic module bears Most of the chip functions are implemented, such as PCIe protocol implementation, channel management and arbitration functions, chip configuration functions, etc.; the Packet Ram module mainly provides data buffering.
Redundant system structure
The redundant display system adopts a dual-host backup system. When one host has a fatal problem at work and cannot recover, another host takes over all its services. The structure of the system adopts the current general industrial computer platform PICMG1.3 specification, and a PEX8696 is placed in the system backplane. At the same time, two PICMG1.3-compliant slots and 16 PCIe×4 slots are designed in the backplane. The video input card can be compatible with a variety of video signal input, including RGB, Video and other signals; video output uses GPU card for hardware acceleration and other image processing, supporting multi-channel output. The architecture block diagram of the system is shown in Figure 2. The current PCIe expansion technology is used to expand the PCIe bus out of 16×4 PCIe channels, of which 8×4 channels are used for video data input and 8×4 channels are used for GPU ( The image processing unit) processes the display. The uplink port uses two x16 PCIe channels to connect HOST1 and HOST2, and the two hosts exchange information through the doorbell register of the bridge chip PEX8696. When HOST1 has a fatal error and cannot work normally, you can preset the flow in the program and pass this information to HOST2 through the doorbell register. After receiving this message, HOST2 starts the reset operation and reconfigures the bridge chip. At that time, it is originally HOST1. All video input and GPU cards controlled will enter the supervision of HOST2 through the reconfiguration of the channel, and at the same time achieve high reliability of the system.
The state transition diagram of the host is shown in Figure 3 [3]. When any host is powered on, it enters the competition and detects the state. The competition principle is that the initiator is the host first; the latter initiator is the standby machine. State transition methods include:
(1) Through self-test, if the host finds that it has a fault, in the condition that the heartbeat register and the standby machine are normal, the doorbell register is notified to the standby machine to be promoted to the host, and the fault state itself is changed;
(2) If the host fails, the heartbeat information and related information cannot be sent to the standby machine within the specified time. The standby machine is automatically transferred to the host state after verifying that the host has abandoned the active state.
(3) The standby machine self-test finds that the fault page--] is transferred to the fault state;
(4) The device entering the fault state gives an alarm message, and after being repaired, enters the competition state again.
The PEX8696 has some special register functions, including a doorbell register and a heartbeat message. The doorbell register is used to send an interrupt from one side of the non-transparent bridge to the other. Both sides of the non-transparent bridge generally have software-controllable interrupt request registers and corresponding interrupt mask registers. These registers are accessible on both sides of the opaque bridge. Heartbeat messages generally come from the master to the slave on the device side and can be used to indicate that it is still alive. The slave host can monitor the state of the master master and if it finds an error, it can take some necessary actions. A heartbeat message can be transmitted through the doorbell register. When the slave host does not receive a certain number of predetermined heartbeat messages, the master of the master device can be considered to be in error. In this system, the special function of the above register is used to realize the monitoring and working state conversion of the host. The following describes the process of taking over the host 1 by the host 2 after the system fails.
When host 1 is operating, host 2 is in standby mode. The two hosts communicate through heartbeat messages. During normal operation, the host processor performs all normal duties because it actively manages the system. In addition, it also needs to periodically send heartbeat messages to the backup processor. The heartbeat message is a sign of whether the processor that initiated the message is healthy or not. Heartbeat messages also protect certain data in the system design to reduce the possibility of false alarms. The heartbeat message assumes the task of verifying that the host processor is functioning properly for the backup processor. This data also provides the latest activity and status of all peripherals. If the backup host cannot receive the heartbeat message [4] in time, it will begin to take control. First, it reduces the port in host 1 to the downstream port to prevent the processor that has sent the failure from interacting with other parts of the system. The conversion is done by using the register CSR (space configuration register) memory provided by the BAR (base address register) in the non-transparent bridge port for address mapping [5] to reprogram the CSR of the switch; then, the host 2 needs to be The port is configured as an uplink port, and the port of the host 1 is configured as a non-transparent bridge port, and the link of the host 1 is removed; then, the host 2 restarts the device in the master host 1 by operating the bridge control register; finally, After clearing all the transactions left in the queue or the incomplete state left by the failure of host 1, host 2 re-enumerates all devices. After enumeration, the system starts to run normally.
Conclusion
This paper mainly aims at the application of high-reliability high-definition large-screen in the fields of medical treatment and monitoring, and specially designed a dual-host redundant system. The system adopts the latest PCIe bus technology, combined with PLX's highly flexible transparent bridge chip and non-transparent bridge technology, which greatly improves the stability of the system without changing the internal design of the conventional video display system. The system failure rate is reduced to 50%; at the same time, the system uses a bridge chip with 96 PCIe channels, which greatly reduces the use of the bridge chip and reduces the cost of the system.
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