For applications where timing is critical, such as video processing, leveraging pure hardware solutions can significantly boost the performance of Xilinx FPGAs. In modern systems, especially those involving real-time video streams, minimizing reconfiguration time is essential to prevent image loss or visible flicker. Partial reconfiguration allows a portion of the FPGA to be updated without disrupting the rest of the system, making it ideal for dynamic and time-sensitive tasks.
To ensure the human eye doesn’t detect any flicker, the reconfiguration process must complete within 40 milliseconds. However, this timeframe is often too short for full device reconfiguration, especially on larger FPGAs. That’s why partial reconfiguration has become a key technique—it reduces the bitstream size, thereby decreasing the time required for updates. Our team at Sagem DS has developed a high-speed partial reconfiguration solution that enables faster and more efficient FPGA updates.
We tested our approach using the Xilinx ML507 development board, which features a Virtex-5 FPGA (XC5VFX70T-FFG1136), a CPLD for routing, and two XCF32P flash memories. This setup allowed us to validate the performance of our hardware-based partial reconfiguration method under real-world conditions.
When it comes to implementing partial reconfiguration, many solutions rely on embedded processors like MicroBlaze or external controllers. While these options are viable, they introduce additional complexity, resource consumption, and latency. By contrast, we opted for a pure hardware solution based on a small state machine, utilizing the Internal Configuration Access Port (ICAP) interface. This approach eliminates delays, uses minimal resources (less than 300 LUTs), and provides precise control over the reconfiguration timing.
Development Process Overview Our workflow follows the standard Xilinx tutorial and user guides for partial reconfiguration. It involves defining reconfigurable regions (RPs) in PlanAhead and importing reconfigurable modules (RMs). Static logic from previous configurations can also be reused, streamlining the process. The entire flow avoids the need for an embedded processor, keeping the design simple and efficient.
During partial reconfiguration, the FPGA must operate in slave mode, with access limited to JTAG, Slave SelectMap, or ICAP interfaces. To speed up the process, we avoided using serial interfaces. Instead, we focused on SelectMap and ICAP. While SelectMap is useful for initial configuration, it lacks clear signals to indicate when the reconfiguration is complete, making it less reliable for partial updates.
This is why we ultimately chose to use ICAP for loading partial bitstreams. Unlike SelectMap, ICAP gives full control to the user after the initial boot, allowing for better monitoring and timing accuracy. One major advantage of ICAP is its ability to reflect the FPGA’s status continuously, enabling users to know exactly when the reconfiguration is finished.
Reconfiguration Features and Components In our video processing applications, we utilize logic elements, BRAMs, and DSP slices. Understanding how each component affects reconfiguration time is crucial for optimizing the size of the reconfigurable area. We conducted extensive testing on the ML507 board to determine the best balance between performance and efficiency.
As shown in Figure 1, we used an external PLL as the reference clock for partial reconfiguration. Although some connections were dictated by the board layout, we ensured the clock frequency was set to 33MHz—the maximum supported by the XCF32P memories. The data bus was 8 bits wide, achieving transfer rates up to 264Mbps, which is sufficient for most real-time video applications.
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