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One of the key factors in achieving high reliability, high performance and long life for battery packs designed into HEV, PHEV and EV powertrains is the electronic components used in battery management systems (BMS). To date, most battery pack designs have adopted centralized, practical BMS hardware that is limited to larger assemblies. In particular, the electrical noise working environment of batteries and related equipment imposes very stringent requirements on data communication links, while the communication links carry the transmission of critical information within the vehicle. A wide range of CANbus can handle this type of noise, but the data throughput requirements of the original BMS data and the associated component costs result in the inability to adopt modular and distributed battery modules in a structured, attractive design, especially in providing a good distribution weight. on. The use of the standard chip-level serial peripheral interface (SPI) isoSPITM physical layer adaptive technology frees up the full potential of this cost-effective distributed battery stack architecture.
How does the isoSPI interface work?
To solve complex interference problems, the main technique used is to “balance†the two-wire (both lines are not grounded) differential signals. This allows noise to appear on the wire, but because the noise on the two wires (common mode) is almost the same, the transmitted differential mode signals are relatively unaffected by each other. In order to deal with very large common mode noise intrusion, isolation methods are also needed. The simplest method is to achieve magnetic coupling by a slim transformer. The transformer windings couple important differences in information across the dielectric barrier, but because of the electrical isolation, the common mode noise is not strongly coupled. These are the same methods used in the very successful Ethernet twisted pair standard. The last aspect is to adjust the signal transmission scheme accordingly to provide a full-duplex SPI activity conversion that can support signal rates up to 1 Mbps, while transmission requires only a single twisted pair. Figure 1 shows the ideal isoSPI differential waveform, which depicts a DC-free pulse that can be coupled through a transformer without loss of information. Different state changes of the traditional SPI signal are encoded by the width, polarity and timing of the pulse.
Figure 1: The isoSPI differential signal encodes the SPI state change on the twisted pair
By adopting all of these technologies, isoSPI supports error-free transmission from the outset of design and performs rigorous high current injection (BCI) interference testing. In practice, Linear Technology demonstrated the full performance in the face of the ultra-durable 200mA BCI, and the same demonstration was performed at several major automotive companies. The isoSPI link is perfectly suited for automotive chassis bus applications. Not only does isoSPI provide inter-module communication, but it is much less expensive than other on-board isolation methods. The safe operation of battery systems in high-voltage environments requires isolation, which provides additional cost savings.
Reduce complexity with isoSPI
Building a BMS usually involves connecting an analog-to-digital converter (ADC) front-end device to the processor, which is to interface with the CANbus link for message exchange within the car. Figure 2 (a) shows a similar structure that requires only two ADC devices to support a traditional SPI data connection. When using SPI signals, thorough galvanic isolation for safety and data integrity needs requires a dedicated data isolation unit for each ADC unit. This can be used to float battery packs from microprocessor systems and CANbus networks using magnetic, capacitive or optical methods, but because they have to handle four signal paths, they are quite expensive components.
(a)
(b)
Figure 2: Traditional BMS isolation and isoSPI methods
Figure 2 (b) shows the same functionality, but with isoSPI. A small, low-cost transformer replaces the data isolator to achieve electrical isolation between the main processor unit and the battery pack. On the main microprocessor side, a small adapter IC (LTC6820) provides the isoSPI host interface. The ADC device shown (LTC6804-2) has integrated isoSPI slave support, so the only circuit that must be added is the correct termination resistance required to balance the transmission line structure. Although only two ADC units are shown in the figure, an extended isoSPI bus can serve 16 units.
Figure 3: Another BMS configuration with isoSPI daisy chain
isoSPI devices support multi-drop bus or point-to-point daisy chain
The isoSPI link works very well with a simple point-to-point connection. As shown in Figure 3, the dual-port ADC device (LTC6804-1) is capable of forming a fully isolated daisy chain structure. The bus or daisy-chain approach has similar overall structural complexity, so different designs tend to adopt one of these methods based on some subtle differences. The daisy-chain method costs slightly lower. It does not require address setting. It generally uses a simpler transformer coupling; the parallel addressable bus has better fault tolerance.
Dividing the BMS electronic system
The example circuit shown in Figures 2 and 3 uses a central architecture, which is a typical BMS design. However, the centralized architecture does not take advantage of one of the main isoSPI features, which is to operate with very long exposed wiring. Traditional SPI connections are not suitable for this task, so current battery systems need to be tailored to the communication limitations in electronic systems. With the isoSPI solution, these design constraints are avoided and a better and better mechanical structure can be achieved.
Figure 4 (a) shows a distributed daisy-chain BMS architecture that supports arbitrary modularization and functionality in a distributed network. To meet the requirements of distributed circuits, the network may have many ADC devices (LTC6804-1) and wire-level interconnects. Using an isoSPI network for ADC information means that all data processing can be combined into a single microprocessor circuit, even without the need to be in the same location as any battery unit. This overall network flexibility is based on isoSPI's BMS system design for high performance and improved price/performance.
Figure 4 (b) shows a distributed BMS architecture using isoSPI in a multi-drop bus. Although externally similar to Figure (a) (including automotive wiring), the isoSPI transmission line is actually a signal pair that connects all of the ADC devices (up to 16 LTC6804-2) in parallel and terminates only the terminals of the bus. Some buses are actually inside the module, but eventually detach again to propagate to the next module.
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