Texas Instruments ( TI ) today announced the industry's widest bandwidth fully integrated transmit/receive processor with 3G / 4G wireless base stations, wireless RF modules and digital pre-distortion ( DPD ) for government communications systems. The GC533x system is equipped with three ready-to-use processors that provide a complete and highly flexible digital transmission and reception solution for broadband and multi-antenna wireless base stations. The cost is much lower than that of high-gate FPGAs. Time and cost of developing an ASIC solution. A complete system evaluation and reference design kit is also available, which will be presented at TI Mobile Congress.
The GC533x family achieves a 148 MHz fifth-order modified transmission bandwidth with Crest reduction (CFR) capability, a wideband digital up/down converter, a fractional resampler, a 48-bit numerically controlled oscillator (NCO) and Automatic gain control supports four transmit antennas and eight receive antennas simultaneously. Combined with the low-cost, high-performance TMS320C6748 floating-point DSP, the GC533x platform provides a high-performance adaptive DPD algorithm or allows customers to implement their own DPD IP capabilities.
Important features and benefits
148 MHz between the two transceivers with a fifth-bit modified DPD bandwidth and a CFR of 2 dB, which is superior to competing solutions, achieving 40% power amplifier performance in three-carrier LTE operation, adjacent channel leakage ratio The (ACLR) is 54 dB and the output is 48 dBm.
· ACLR is 20 dB higher than uncorrected signals for broadband applications, and 40 dB higher than for narrowband applications, while providing multi-channel, multi-carrier for 3GPP, MC-GSM, WiMAX, WiBRO and 3GPP2 standards , multi-mode and multi-frequency support.
· Interface with four transmit antennas and eight receive antennas, as well as real or complex observation paths, not only enables 2x2, 2x4, 4x4, and 4x8 transmit/receive solutions, but also simplifies board configuration and costs ten times less than FPGAs .
· With 48 digital up/down conversion channels for data rates up to 184 MS/s, with a four-component resampler, 48-bit NCO and a large number of up-converters for extended frequency and The flexibility of frequency planning.
· Integrated I/Q imbalance correction improves the performance of broadband complex receive and DPD observation signal chains, reducing the sampling rate and cost of receiving and returning analog-to-digital converters (ADCs).
Tools and support
The GC5330SEK System Evaluation and Reference Design Kit provides a complete transceiver reference design for broadband applications, including:
· DAC3283 communication DAC (digital to analog converter), TRF372017 IQ modulator integrated with PLL/VCO, and TRF370417 IQ modulator for diversity transmission
· PGA870 programmable gain amplifier, THS770006 fully differential operational amplifier, and ADS62P49 ADC for diversity transmission
· DPD-backed PGA870 and ADS41B49 ADC
· System frequency CDCE72010 frequency synthesizer and jitter cleaner
TMS320C6748 fixed point / floating point DSP
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