The semiconductor industry is rapidly moving toward super-integration, a trend that has sparked new conversations around the complex relationship between 3D IC design and power integrity. Traditionally, engineers have focused on adding features to a single die, but integrating multiple functions into one chip presents significant challenges. Enter 3D ICs—stacking modules and using interposers is becoming a key solution. One of the most popular applications today involves combining high-bandwidth memory with the processor in close proximity, enabling faster communication through low-impedance, high-parallel connections between the DRAM stack and main memory.
Of course, every innovation brings new challenges. Power integrity at the package and board level is now a critical concern. While traditional approaches treat power integrity as a core-by-core issue, the reality is more complex. High impedance between packages and the increasing operating frequencies of chips reduce the impact of inter-chip communication on on-chip power noise. However, modern systems now involve a wide range of resonant frequencies—from MHz at the board level, to 100 MHz in the interposer/TSV layers, and up to GHz at the chip level. These characteristics can significantly affect power integrity, making it impossible to ignore even the intermediate frequency ranges.
As a result, power integrity analysis can no longer assume that each chip operates independently. It must be evaluated across the entire 3D IC package. A recent webinar highlighted this exact challenge, emphasizing two main components: first, building a precise power model for the whole 3DIC device, suitable for detailed transient and AC Spice analysis; second, ensuring that the model captures a broad frequency response, from MHz at the board/package level to GHz at the chip level.
Creating an accurate power model requires attention to several levels. Chip and die-level analysis is well-established, with tools like RedHawk and Totem (for analog designs) being widely used. RedHawk is especially effective for interposer extraction, which can be treated as another semiconductor component supported by manufacturing files. For TSV extraction, SIwave or HFSS are recommended. All these elements can then be integrated into a system-on-chip power model (CPM), used for detailed analysis in a chip model analyzer (CMA).
In the second phase of analysis, it's crucial that the CPM reflects the full system response. At the chip level, we often look at activity in the tens of nanoseconds, but larger time scales can introduce significant power fluctuations—such as when a chip transitions from active to idle mode within a 3DIC package, or when external devices on the board change state. Accurate analysis at the nanosecond level within the microsecond range is impractical, so tools like CMA help build a representative power noise spectrum based on both high-frequency chip responses and low-frequency inputs, such as those from interposers, TSVs, and package/board interactions.
To model long-cycle events, methods like analyzing long-term envelopes are used. This can be done by importing data from a PowerArTIst configuration file, manually specifying settings, or generating random noise based on the 3DIC or board PDN’s sensitivity to impedance changes. With such a wide range of resonant frequencies across the system, optimizing the power distribution network (PDN) at the system level is now more important than ever. A broader, more comprehensive approach to analysis is essential to ensure reliable performance in next-generation 3D ICs.
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